usr/src/cmd/pcitool/pcitool.c

755

int last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;

usr/src/cmd/pcitool/pcitool.c

836

last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;

usr/src/uts/common/io/fibre-channel/fca/qlc/ql_xioctl.c

1465

((ha->pci_bus_addr & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT);

usr/src/uts/common/sys/pci.h

1198

#define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT)

usr/src/uts/common/sys/pci.h

1205

(uint_t)(d) << PCI_REG_DEV_SHIFT | \

usr/src/uts/i86pc/io/pci/pci_tools.c

1119

((prg.dev_no & (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) !=

usr/src/uts/i86pc/io/pci/pci_tools.c

58

#define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA)

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

105

reg.pci_phys_hi += 1 << PCI_REG_DEV_SHIFT;

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

52

reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

69

reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

81

reg.pci_phys_hi = 21 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=21, Func=0 */

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

88

reg.pci_phys_hi = 22 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=22, Func=0 */

usr/src/uts/sun4/io/px/px_tools.c

440

(PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != prg->dev_no) ||

usr/src/uts/sun4/io/px/px_tools_var.h

47

((p_p)->dev_no << PCI_REG_DEV_SHIFT) + \

usr/src/uts/sun4u/io/pci/pci_tools.c

712

(PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != prg->dev_no) ||

usr/src/uts/sun4u/io/pci/pci_tools.c

880

(prg.dev_no << PCI_REG_DEV_SHIFT) +

usr/src/uts/sun4u/io/pci/pci_tools.c

891

prg.bus_no << PCI_REG_BUS_SHIFT, prg.dev_no << PCI_REG_DEV_SHIFT,