PCI_MEM_PUT32
PCI_MEM_PUT32(softs, device,
PCI_MEM_PUT32(softs, device, (uint32_t)(slotp->fib_phyaddr >> 32));
PCI_MEM_PUT32(softs, device, slotp->acp->fib_size);
PCI_MEM_PUT32(softs, AAC_IQUE, index);
PCI_MEM_PUT32(softs, AAC_OIMR, ~AAC_DB_INTR_NEW); \
PCI_MEM_PUT32(softs, AAC_OIMR, ~AAC_DB_INTR_BITS); \
PCI_MEM_PUT32(softs, AAC_OIMR, ~0); \
#define AAC_STATUS_CLR(softs, mask) PCI_MEM_PUT32(softs, AAC_ODBR, mask)
#define AAC_NOTIFY(softs, val) PCI_MEM_PUT32(softs, AAC_IDBR, val)
#define AAC_OUTB_SET(softs, val) PCI_MEM_PUT32(softs, AAC_OQUE, val)
PCI_MEM_PUT32(softs, AAC_IRCSR, AAC_IRCSR_CORES_RST);
PCI_MEM_PUT32(softs, AAC_RX_MAILBOX, cmd);
PCI_MEM_PUT32(softs, AAC_RX_MAILBOX + 4, arg0);
PCI_MEM_PUT32(softs, AAC_RX_MAILBOX + 8, arg1);
PCI_MEM_PUT32(softs, AAC_RX_MAILBOX + 12, arg2);
PCI_MEM_PUT32(softs, AAC_RX_MAILBOX + 16, arg3);
PCI_MEM_PUT32(softs, AAC_RKT_MAILBOX, cmd);
PCI_MEM_PUT32(softs, AAC_RKT_MAILBOX + 4, arg0);
PCI_MEM_PUT32(softs, AAC_RKT_MAILBOX + 8, arg1);
PCI_MEM_PUT32(softs, AAC_RKT_MAILBOX + 12, arg2);
PCI_MEM_PUT32(softs, AAC_RKT_MAILBOX + 16, arg3);
PCI_MEM_PUT32(softs,
PCI_MEM_PUT32(softs,