PCI_CONF_BASE4
{ PCI_CONF_BASE4, 4, "BAR4", "Base Address Register 4 (@20)" },
pci_config_get32(config_handle, PCI_CONF_BASE4),
w32l = PCICFG_RD32(qlt, PCI_CONF_BASE4);
w32h = PCICFG_RD32(qlt, PCI_CONF_BASE4);
pciconfig_bar(Adapter, PCI_CONF_BASE4, "PCI_CONF_BASE4");
chs.chs_base4 = ql_pci_config_get32(ha, PCI_CONF_BASE4);
ql_pci_config_put32(ha, PCI_CONF_BASE4, chs_p->chs_base4);
pci_config_get32(qlge->pci_handle, PCI_CONF_BASE4);
pci_config_get32(handle, PCI_CONF_BASE4));
pci_config_get32(handle, PCI_CONF_BASE4));
pci_config_get32(pwp->pci_acc_handle, PCI_CONF_BASE4));
chsp->chs_base4 = pci_config_get32(confhdl, PCI_CONF_BASE4);
pci_config_put32(confhdl, PCI_CONF_BASE4, chs_p->chs_base4);
pci_config_get32(config_handle, PCI_CONF_BASE4));
pci_config_get32(config_handle, PCI_CONF_BASE4));
PCI_CONF_BASE4,
(off_t)(p_offset + PCI_CONF_BASE4))) & ~DB_IO_BIT));
ph->bar4 = pci_config_get32(config_handle, hdr_off + PCI_CONF_BASE4);
PCI_CONF_BASE4,
#define DB_PCONF_DS_MEM3 PCI_CONF_BASE4
#define DB_PCONF_US_MEM2 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE4
#define DB_SCONF_US_MEM2 PCI_CONF_BASE4
#define DB_SCONF_DS_MEM3 DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE4