usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5327

for (uint32_t i = 0; i < PCI_CAP_PTR_OFF / 4; i++) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5333

walk.pcw_valid = PCI_CAP_PTR_OFF;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5334

walk.pcw_caplen = PCI_CAP_PTR_OFF;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5367

pcieadm_cfgspace_write(fd, &data.pcb_u8[0], PCI_CAP_PTR_OFF);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5392

for (uint32_t i = PCI_CAP_PTR_OFF / 4; i < PCI_CONF_HDR_SIZE / 4; i++) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5402

pcieadm_cfgspace_write(fd, &data.pcb_u8[PCI_CAP_PTR_OFF],

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5403

PCI_CONF_HDR_SIZE - PCI_CAP_PTR_OFF);

usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c

3020

while (offset >= PCI_CAP_PTR_OFF) {

usr/src/uts/common/io/pciex/pci_props.c

457

for (; max_cap > 0 && cap_off >= PCI_CAP_PTR_OFF; max_cap--) {

usr/src/uts/common/io/sata/adapters/ahci/ahci.c

4308

if (caps_ptr < PCI_CAP_PTR_OFF) {

usr/src/uts/i86pc/io/immu_dvma.c

574

while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) {

usr/src/uts/intel/io/pci/pci_boot.c

2214

while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {

usr/src/uts/intel/io/pciex/pcie_nvidia.c

67

while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) {