usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5398

walk.pcw_valid = PCIE_EXT_CAP;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5463

for (uint_t i = PCIE_EXT_CAP / 4; i < PCIE_CONF_HDR_SIZE / 4; i++) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5472

pcieadm_cfgspace_write(fd, &data.pcb_u8[PCIE_EXT_CAP],

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5473

PCIE_CONF_HDR_SIZE - PCIE_EXT_CAP);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5477

cap = PCIE_EXT_CAP;

usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c

3062

eoffset = PCIE_EXT_CAP;

usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c

3064

while (eoffset >= PCIE_EXT_CAP) {

usr/src/uts/common/io/pci_cap.c

185

for (base = PCIE_EXT_CAP; base; base = (xcaps_hdr >>

usr/src/uts/common/io/pci_cap.c

94

for (base = PCIE_EXT_CAP; base && i < index; i++) {

usr/src/uts/common/io/pciex/pcie.c

2027

for (base = PCIE_EXT_CAP; base; base = (capid >>