usr/src/cmd/pcieadm/pcieadm_cfgspace.c

162

uint8_t pcb_u8[PCIE_CONF_HDR_SIZE];

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

163

uint32_t pcb_u32[PCIE_CONF_HDR_SIZE / 4];

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

392

VERIFY3U(off, <, PCIE_CONF_HDR_SIZE);

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5463

for (uint_t i = PCIE_EXT_CAP / 4; i < PCIE_CONF_HDR_SIZE / 4; i++) {

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5469

walk.pcw_valid = PCIE_CONF_HDR_SIZE;

usr/src/cmd/pcieadm/pcieadm_cfgspace.c

5473

PCIE_CONF_HDR_SIZE - PCIE_EXT_CAP);

usr/src/uts/common/os/sunpci.c

346

regbuf = (uint32_t *)kmem_zalloc((size_t)PCIE_CONF_HDR_SIZE,

usr/src/uts/common/os/sunpci.c

353

maskbufsz = (size_t)((PCIE_CONF_HDR_SIZE/ sizeof (uint32_t)) >>

usr/src/uts/common/os/sunpci.c

359

for (i = 0; i < (PCIE_CONF_HDR_SIZE / sizeof (uint32_t)); i++) {

usr/src/uts/common/os/sunpci.c

389

(size_t)PCIE_CONF_HDR_SIZE)) != DDI_PROP_SUCCESS) {

usr/src/uts/common/os/sunpci.c

398

kmem_free(regbuf, (size_t)PCIE_CONF_HDR_SIZE);

usr/src/uts/common/os/sunpci.c

730

ASSERT(elements == PCIE_CONF_HDR_SIZE);

usr/src/uts/common/os/sunpci.c

733

for (i = 0; i < PCIE_CONF_HDR_SIZE / sizeof (uint32_t); i++) {

usr/src/uts/i86pc/io/pci/pci_tools.c

104

max_cfg_size = PCIE_CONF_HDR_SIZE;

usr/src/uts/i86pc/io/pci/pci_tools.c

1132

if (max_cfg_size == PCIE_CONF_HDR_SIZE)

usr/src/uts/i86pc/io/pciex/npe.c

607

pci_rp->pci_size_low = PCIE_CONF_HDR_SIZE;

usr/src/uts/i86pc/io/pciex/npe.c

721

pci_rp->pci_size_low = PCIE_CONF_HDR_SIZE;

usr/src/uts/intel/io/intel_nb5000/nb_pci_cfg.c

56

reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */

usr/src/uts/intel/io/intel_nhm/nhm_pci_cfg.c

55

reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */

usr/src/uts/sun4/io/px/px.c

772

if ((off >= PCIE_CONF_HDR_SIZE) ||

usr/src/uts/sun4/io/px/px.c

773

(len > PCIE_CONF_HDR_SIZE) ||

usr/src/uts/sun4/io/px/px.c

774

(off + len > PCIE_CONF_HDR_SIZE))