PCICFG_OFFSET
val = REG_RD(pdev, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
lm_reg_rd_ind(pdev,PCICFG_OFFSET + bar_address,&bar_size);
pdev->hw_info.grc_didvid = REG_RD(pdev, (PCICFG_OFFSET + PCICFG_VENDOR_ID_OFFSET));
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_CONTROL_5, (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
REG_WR(pdev,PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
static const u32_t pcicfg_device_control_offset = PCICFG_OFFSET + PCICFG_DEVICE_CONTROL;
static const u32_t pcicfg_device_control_offset = PCICFG_OFFSET + PCICFG_DEVICE_CONTROL;