NXGE_REG_WR64
NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0x1);
NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0);
NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val);
NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val);
NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val);
NXGE_REG_WR64(handle, IPP_REG_ADDR(portn, reg), val);\
NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val))
NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val))
NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val))
NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val))
NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val))
NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
NXGE_REG_WR64(handle, pre_offset, clr.value);
NXGE_REG_WR64(handle, sha_offset, clr.value);
NXGE_REG_WR64(handle, pre_offset, clr.value);
NXGE_REG_WR64(handle, sha_offset, clr.value);
NXGE_REG_WR64(handle, addr_offset, addr.value);
NXGE_REG_WR64(handle, d0_offset, d0.value);
NXGE_REG_WR64(handle, d1_offset, d1.value);
NXGE_REG_WR64(handle, d2_offset, d2.value);
NXGE_REG_WR64(handle, d3_offset, d3.value);
NXGE_REG_WR64(handle, d4_offset, d4.value);
NXGE_REG_WR64(handle, addr_offset, addr.value);
NXGE_REG_WR64(handle, offset, clk_div.value);
NXGE_REG_WR64(handle, offset, rand_reg.value);
NXGE_REG_WR64(handle, offset, rand_reg.value);
NXGE_REG_WR64(handle, offset, md_reg.value);
NXGE_REG_WR64(handle, offset, md_reg.value);
NXGE_REG_WR64(handle, offset, md_reg.value);
NXGE_REG_WR64(handle, offset, md_reg.value);
NXGE_REG_WR64(handle, offset, wt_reg.value);
NXGE_REG_WR64(handle, offset, wred_reg.value);
NXGE_REG_WR64(handle, offset, rdc_tbl.value);
NXGE_REG_WR64(handle, offset, tbl_reg.value);
NXGE_REG_WR64(handle, offset, intr_mask.value);
NXGE_REG_WR64(handle, valid_offset, page_vld.value);
NXGE_REG_WR64(handle, valid_offset, page_vld.value);
NXGE_REG_WR64(handle, mask_offset, page_mask.value);
NXGE_REG_WR64(handle, value_offset, page_value.value);
NXGE_REG_WR64(handle, reloc_offset, page_reloc.value);
NXGE_REG_WR64(handle, valid_offset, page_vld.value);
NXGE_REG_WR64(handle, offset, page_hdl.value);
NXGE_REG_WR64(handle, offset, cfg.value);
NXGE_REG_WR64(handle, offset, cnt->value);
NXGE_REG_WR64(handle, offset, cnt.value);
NXGE_REG_WR64(handle, TXC_INT_STAT_REG, istatus);
NXGE_REG_WR64(handle, TXC_INT_MASK_REG, val);
NXGE_REG_WR64(handle, TXC_CONTROL_REG,
NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value);
NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value);
NXGE_REG_WR64(handle, TXC_PORT_CTL_REG, TXC_PORT_CNTL_CLEAR);
NXGE_REG_WR64(handle, TXC_TRAINING_REG, (uint64_t)vector);
NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | (1 << port));
NXGE_REG_WR64(handle, TXC_CONTROL_REG, (val & ~(1 << port)));
NXGE_REG_WR64(handle, TXC_MAX_REORDER_REG, val);
NXGE_REG_WR64(handle, \
NXGE_REG_WR64(handle, \
NXGE_REG_WR64(handle, offset, 0);
NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0);
NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value);
NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value);
NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value);
NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value);
NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
NXGE_REG_WR64(handle, offset, (uint64_t)ldf_mask);
NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg),
NXGE_REG_WR64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg),
NXGE_REG_WR64(handle, LDGITMRES_REG, (res & LDGTITMRES_RES_MASK));
NXGE_REG_WR64(handle, SID_REG + LDG_SID_OFFSET(sid.ldg), sd.value);
NXGE_REG_WR64(handle, SYS_ERR_MASK_REG, mask);
NXGE_REG_WR64(handle, RST_CTL_REG, rst.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value);
NXGE_REG_WR64(handle, MULTI_PART_CTL_REG, mp.value);
NXGE_REG_WR64(handle, DMA_BIND_REG +
NXGE_REG_WR64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld),
NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val);
NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val);
NXGE_REG_WR64(handle, ZCP_INT_STAT_REG, val);
NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val);
NXGE_REG_WR64(handle, ZCP_BAM4_RE_CTL_REG, region_attr->value);
NXGE_REG_WR64(handle, ZCP_BAM8_RE_CTL_REG, region_attr->value);
NXGE_REG_WR64(handle, ZCP_BAM16_RE_CTL_REG, region_attr->value);
NXGE_REG_WR64(handle, ZCP_BAM32_RE_CTL_REG, region_attr->value);
NXGE_REG_WR64(handle, ZCP_DST4_RE_CTL_REG, val);
NXGE_REG_WR64(handle, ZCP_DST8_RE_CTL_REG, val);
NXGE_REG_WR64(handle, ZCP_DST16_RE_CTL_REG, val);
NXGE_REG_WR64(handle, ZCP_DST32_RE_CTL_REG, val);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, offset, cfifo_reg.value);
NXGE_REG_WR64(handle, ZCP_RAM_ACC_REG, ram_ctl.value);
NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val);
NXGE_REG_WR64(handle, ZCP_RAM_DATA0_REG, val->w0);
NXGE_REG_WR64(handle, ZCP_RAM_DATA1_REG, val->w1);
NXGE_REG_WR64(handle, ZCP_RAM_DATA2_REG, val->w2);
NXGE_REG_WR64(handle, ZCP_RAM_DATA3_REG, val->w3);
NXGE_REG_WR64(handle, ZCP_RAM_DATA4_REG, val->w4);
NXGE_REG_WR64(handle, ZCP_RAM_BE_REG, ram_en.value);
NXGE_REG_WR64(handle, ZCP_RAM_ACC_REG, ram_ctl.value);
NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val);
NXGE_REG_WR64(nxge->npi_handle, offset, mgm.value);
NXGE_REG_WR64(handle,
NXGE_REG_WR64(handle,
NXGE_REG_WR64(handle,
NXGE_REG_WR64(handle,
NXGE_REG_WR64(nxgep->npi_handle,
NXGE_REG_WR64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG,
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0);
NXGE_REG_WR64(nxgep->npi_handle,
NXGE_REG_WR64(nxgep->npi_handle,
NXGE_REG_WR64(nxgep->npi_handle,
NXGE_REG_WR64(nxgep->npi_handle,
NXGE_REG_WR64(nxgep->npi_handle, ZCP_INT_STAT_TEST_REG,
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0);
NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0);
NXGE_REG_WR64((handle), (offset), (value))