NXGE_REG_RD64
NXGE_REG_RD64(handle, ESPC_MAC_ADDR_0, &mac0.value);
NXGE_REG_RD64(handle, ESPC_MAC_ADDR_1, &mac1.value);
NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val);
NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val);
NXGE_REG_RD64(handle, ESPC_MOD_STR_LEN, &val);
NXGE_REG_RD64(handle, ESPC_MOD_STR(j), &val);
NXGE_REG_RD64(handle, ESPC_BD_MOD_STR_LEN, &val);
NXGE_REG_RD64(handle, ESPC_BD_MOD_STR(j), &val);
NXGE_REG_RD64(handle, ESPC_PHY_TYPE, &phy.value);
NXGE_REG_RD64(handle, ESPC_PHY_TYPE, &phy.value);
NXGE_REG_RD64(handle, ESPC_MAX_FM_SZ, &val);
NXGE_REG_RD64(handle, ESPC_VER_IMGSZ, &val);
NXGE_REG_RD64(handle, ESPC_VER_IMGSZ, &val);
NXGE_REG_RD64(handle, ESPC_CHKSUM, &val);
NXGE_REG_RD64(handle, ESPC_INTR_NUM, &intr.value);
NXGE_REG_RD64(handle, ESPC_NCR_REGN(i), &val);
NXGE_REG_RD64(handle, ESPC_NCR_REGN(reg_idx), &val);
NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val);
NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val);
NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, IPP_REG_ADDR(portn, reg), val);\
NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
NXGE_REG_RD64(handle, pre_offset, &pre_log->value);
NXGE_REG_RD64(handle, sha_offset, &sha_log->value);
NXGE_REG_RD64(handle, pre_offset, &clr.value);
NXGE_REG_RD64(handle, sha_offset, &clr.value);
NXGE_REG_RD64(handle, d4_offset, &d4.value);
NXGE_REG_RD64(handle, d3_offset, &d3.value);
NXGE_REG_RD64(handle, d2_offset, &d2.value);
NXGE_REG_RD64(handle, d1_offset, &d1.value);
NXGE_REG_RD64(handle, d0_offset, &d0.value);
NXGE_REG_RD64(handle, offset, &rand_reg.value);
NXGE_REG_RD64(handle, offset, &md_reg.value);
NXGE_REG_RD64(handle, offset, &md_reg.value);
NXGE_REG_RD64(handle, offset, &use_reg.value);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, offset, &intr_mask.value);
NXGE_REG_RD64(handle, offset, &stat->value);
NXGE_REG_RD64(handle, rx_fzc_offset[i], &value);
NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
NXGE_REG_RD64(handle, valid_offset, &page_vld.value);
NXGE_REG_RD64(handle, offset, &cnt->value);
NXGE_REG_RD64(handle, offset, &cnt.value);
NXGE_REG_RD64(handle, TXC_INT_STAT_REG, &status.value);
NXGE_REG_RD64(handle, TXC_INT_MASK_REG, &val);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, txc_fzc_offset[i], &value);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value);
NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK),
NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val);
NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val);
NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val);
NXGE_REG_RD64(handle, \
NXGE_REG_RD64(handle, \
NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value);
NXGE_REG_RD64(handle, tx_fzc_offset[i], &value);
NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
NXGE_REG_RD64(handle, offset, &sv);
NXGE_REG_RD64(handle, pio_offset[i], &value);
NXGE_REG_RD64(handle, offset, &val);
NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val);
NXGE_REG_RD64(handle, fzc_pio_offset[i], &value);
NXGE_REG_RD64(handle, LDGIMGN_REG + LDSV_OFFSET(ldg), &val);
NXGE_REG_RD64(handle, (LDGIMGN_REG + LDSV_OFFSET(ldg)), &mgm.value);
NXGE_REG_RD64(handle, LDGITMRES_REG, &val);
NXGE_REG_RD64(handle, (SID_REG + LDG_SID_OFFSET(sid_p->ldg)),
NXGE_REG_RD64(handle, SYS_ERR_STAT_REG, &statp->value);
NXGE_REG_RD64(handle, RST_CTL_REG, &rstp->value);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, RST_CTL_REG, &rst.value);
NXGE_REG_RD64(handle, offset, &value);
NXGE_REG_RD64(handle, offset,
NXGE_REG_RD64(handle, offset,
NXGE_REG_RD64(handle, offset,
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value);
NXGE_REG_RD64(handle, MULTI_PART_CTL_REG, &mpc.value);
NXGE_REG_RD64(handle, DMA_BIND_REG + offset, pValue);
NXGE_REG_RD64(handle, LDG_NUM_REG + LD_NUM_OFFSET(ld), &val);
NXGE_REG_RD64(handle, offset, ldf_p);
NXGE_REG_RD64(handle, ZCP_INT_MASK_REG, &val);
NXGE_REG_RD64(handle, ZCP_INT_STAT_REG, &val);
NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
NXGE_REG_RD64(handle, offset, &cfifo_reg.value);
NXGE_REG_RD64(handle, ZCP_RAM_DATA0_REG, &val->w0);
NXGE_REG_RD64(handle, ZCP_RAM_DATA1_REG, &val->w1);
NXGE_REG_RD64(handle, ZCP_RAM_DATA2_REG, &val->w2);
NXGE_REG_RD64(handle, ZCP_RAM_DATA3_REG, &val->w3);
NXGE_REG_RD64(handle, ZCP_RAM_DATA4_REG, &val->w4);
NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val);
NXGE_REG_RD64(handle, ZCP_RAM_ACC_REG, &val);\
NXGE_REG_RD64(nxge->npi_handle, offset, value);
NXGE_REG_RD64(nxgep->npi_handle, reg, ®data);
NXGE_REG_RD64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG,
NXGE_REG_RD64(nxgep->npi_handle, ZCP_INT_STAT_TEST_REG,
NXGE_REG_RD64((handle), (offset), (val_p))