A_PL_CAUSE
t1_write_reg_4(mac->adapter, A_PL_CAUSE,
u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE);
t1_write_reg_4(adapter, A_PL_CAUSE,
u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
(void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */
u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
t1_write_reg_4(mc3->adapter, A_PL_CAUSE,
t1_write_reg_4(mc3->adapter, A_PL_CAUSE, F_PL_INTR_MC3);
t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4);
t1_write_reg_4(mc5->adapter, A_PL_CAUSE, F_PL_INTR_MC5);
pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE);
t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr);
t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP);
t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP);
t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP);
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT);
t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK);
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_SGE_DATA);