Symbol: A_PL_CAUSE
usr/src/uts/common/io/chxge/com/ch_mac.c
142
t1_write_reg_4(mac->adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/ch_subr.c
1088
u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE);
usr/src/uts/common/io/chxge/com/ch_subr.c
1090
t1_write_reg_4(adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/ch_subr.c
1104
u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
usr/src/uts/common/io/chxge/com/ch_subr.c
1131
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
usr/src/uts/common/io/chxge/com/ch_subr.c
1132
(void) t1_read_reg_4(adapter, A_PL_CAUSE); /* flush writes */
usr/src/uts/common/io/chxge/com/ch_subr.c
224
u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE);
usr/src/uts/common/io/chxge/com/ch_subr.c
257
t1_write_reg_4(adapter, A_PL_CAUSE, cause);
usr/src/uts/common/io/chxge/com/espi.c
145
t1_write_reg_4(espi->adapter, A_PL_CAUSE, F_PL_INTR_ESPI);
usr/src/uts/common/io/chxge/com/mc3.c
101
t1_write_reg_4(mc3->adapter, A_PL_CAUSE,
usr/src/uts/common/io/chxge/com/mc3.c
96
t1_write_reg_4(mc3->adapter, A_PL_CAUSE, F_PL_INTR_MC3);
usr/src/uts/common/io/chxge/com/mc4.c
240
t1_write_reg_4(mc4->adapter, A_PL_CAUSE, F_PL_INTR_MC4);
usr/src/uts/common/io/chxge/com/mc5.c
552
t1_write_reg_4(mc5->adapter, A_PL_CAUSE, F_PL_INTR_MC5);
usr/src/uts/common/io/chxge/com/pm3393.c
247
pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE);
usr/src/uts/common/io/chxge/com/pm3393.c
249
t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr);
usr/src/uts/common/io/chxge/com/tp.c
361
t1_write_reg_4(tp->adapter, A_PL_CAUSE, FPGA_PCIX_INTERRUPT_TP);
usr/src/uts/common/io/chxge/com/tp.c
366
t1_write_reg_4(tp->adapter, A_PL_CAUSE, F_PL_INTR_TP);
usr/src/uts/common/io/chxge/com/ulp.c
56
t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP);
usr/src/uts/common/io/chxge/pe.c
1519
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT);
usr/src/uts/common/io/chxge/sge.c
539
t1_write_reg_4(sge->obj, A_PL_CAUSE, SGE_PL_INTR_MASK);
usr/src/uts/common/io/chxge/sge.c
604
t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_SGE_DATA);