NPI_BLOCK_ID_SHIFT
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) | OPCODE_INVALID |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) | CONFIG_INVALID |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) | COUNTER_INVALID |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) | RESET_FAILED |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((IPP_BLK_ID << NPI_BLOCK_ID_SHIFT) | PORT_INVALID |\
#define NPI_MAC_PORT_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_OPCODE_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_PCS_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_TXMAC_RESET_FAILED(portn) ((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_RXMAC_RESET_FAILED(portn) ((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_CONFIG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_MII_READ_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define NPI_MAC_MII_WRITE_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\
#define RXDMA_ER_ST (RXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT)
#define TXC_ER_ST (TXC_BLK_ID << NPI_BLOCK_ID_SHIFT)
#define TXDMA_ER_ST (TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT)
#define VIR_ERR_ST (VIR_BLK_ID << NPI_BLOCK_ID_SHIFT)