AV_MASK
ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
irqp->airq_rdt_entry |= AV_MASK;
if ((masked = (rdt_entry & AV_MASK)) == 0) {
AV_MASK | rdt_entry);
intin_no, rdt_entry & ~AV_MASK);
irqp->airq_rdt_entry &= ~AV_MASK;
(AV_MASK | rdt_entry));
((~AV_MASK) & rdt_entry));
AV_MASK | irqp->airq_rdt_entry);
apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
if (((lvtval & AV_MASK) == AV_MASK) ||
AV_MASK|APIC_RESV_IRQ);
AV_MASK);
AV_MASK);
if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) {
AV_MASK | rdt_entry);
intin_no, rdt_entry & ~AV_MASK);
ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * i, AV_MASK);
ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK);
apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
if (((lvtval & AV_MASK) == AV_MASK) ||
AV_MASK|APIC_RESV_IRQ);
apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect | AV_MASK);
apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK);
apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK);
apic_reg_ops->apic_write(APIC_INT_VECT1, AV_MASK);
apic_reg_ops->apic_write(APIC_ERR_VECT, AV_MASK);
apic_reg_ops->apic_write(APIC_PCINT_VECT, AV_MASK);
((~AV_MASK) & rdt_entry));
(AV_MASK | rdt_entry));
(apic_clkvect + APIC_BASE_VECT) | AV_MASK);
(apic_clkvect + APIC_BASE_VECT) | AV_MASK);
(apic_clkvect + APIC_BASE_VECT) | AV_MASK);
if ((enable_val & AV_MASK) == AV_MASK)
if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) {
AV_MASK | rdt_entry);
intin_no, rdt_entry & ~AV_MASK);
ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * i, AV_MASK);
ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK);
xpv_apicadr[APIC_LOCAL_TIMER] = AV_MASK;
xpv_apicadr[APIC_INT_VECT0] = AV_MASK; /* local intr reg 0 */