usr/src/uts/intel/io/vmm/intel/vmx.c

3910

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

3911

MSR_VMX_PROCBASED_CTLS2, PROCBASED_CTLS2_ONE_SETTING,

usr/src/uts/intel/io/vmm/intel/vmx.c

3945

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2, MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

487

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

488

MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

498

error = vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

499

MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

551

cap_wbinvd_exit = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

552

MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

556

cap_invpcid = (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

557

MSR_VMX_PROCBASED_CTLS2, PROCBASED2_ENABLE_INVPCID, 0,

usr/src/uts/intel/io/vmm/intel/vmx.c

575

if (vmx_set_ctlreg(MSR_VMX_PROCBASED_CTLS2,

usr/src/uts/intel/io/vmm/intel/vmx.c

576

MSR_VMX_PROCBASED_CTLS2, apicv_bits, 0, &tmp) == 0) {