usr/src/cmd/bhyvectl/bhyvectl.c

1545

MSR_IDENT_MAP(MSR_MTRRcap)

usr/src/uts/intel/io/vmm/vmm.c

1987

case MSR_MTRRcap:

usr/src/uts/intel/io/vmm/vmm.c

2022

case MSR_MTRRcap:

usr/src/uts/intel/io/vmm/vmm.c

2069

case MSR_MTRRcap:

usr/src/uts/intel/io/vmm/vmm.c

2094

case MSR_MTRRcap:

usr/src/uts/intel/io/vmm/vmm.c

2151

case MSR_MTRRcap:

usr/src/uts/intel/io/vmm/vmm.c

4118

MSR_MTRRcap,

usr/src/uts/intel/io/vmm/vmm.c

4166

case MSR_MTRRcap: {

usr/src/uts/intel/io/vmm/vmm.c

4181

ASSERT3U(msr, !=, MSR_MTRRcap);