usr/src/uts/sun4/io/px/px.c

648

if (px_add_msiq_intr(dip, dip, &hdl, MSG_REC,

usr/src/uts/sun4/io/px/px.c

660

PX_INTR_STATE_ENABLE, MSG_REC, PCIE_PME_ACK_MSG) != DDI_SUCCESS) {

usr/src/uts/sun4/io/px/px.c

670

(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,

usr/src/uts/sun4/io/px/px.c

700

(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, PCIE_PME_ACK_MSG,

usr/src/uts/sun4/io/px/px.c

705

PX_INTR_STATE_DISABLE, MSG_REC, PCIE_PME_ACK_MSG);

usr/src/uts/sun4/io/px/px_intr.c

324

case MSG_REC:

usr/src/uts/sun4/io/px/px_intr.c

378

if ((rec_type == MSG_REC) &&

usr/src/uts/sun4/io/px/px_msiq.c

159

if (rec_type == MSG_REC) {

usr/src/uts/sun4/io/px/px_msiq.c

241

if (rec_type == MSG_REC) {

usr/src/uts/sun4/io/px/px_pec.c

164

MSG_REC, (msgcode_t)PCIE_CORR_MSG, -1,

usr/src/uts/sun4/io/px/px_pec.c

176

PX_ERR_LOW_PIL, PX_INTR_STATE_ENABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

187

MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, -1,

usr/src/uts/sun4/io/px/px_pec.c

200

PX_ERR_PIL, PX_INTR_STATE_ENABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

211

MSG_REC, (msgcode_t)PCIE_FATAL_MSG, -1,

usr/src/uts/sun4/io/px/px_pec.c

223

PX_INTR_STATE_ENABLE, MSG_REC, PCIE_FATAL_MSG)) != DDI_SUCCESS) {

usr/src/uts/sun4/io/px/px_pec.c

259

(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

264

PX_ERR_LOW_PIL, PX_INTR_STATE_DISABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

276

(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

281

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

292

(void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC,

usr/src/uts/sun4/io/px/px_pec.c

297

PX_ERR_PIL, PX_INTR_STATE_DISABLE, MSG_REC, PCIE_FATAL_MSG);

usr/src/uts/sun4u/io/px/px_lib4u.c

1031

msiq_rec_p->msiq_rec_type = MSG_REC;