MR_ADDR
status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T),
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL),
(void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC));
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR),
CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR),
reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA));
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg);
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL),
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB);
CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0);
CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB);
CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF);
CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET);
CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK),
CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac);
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL),
CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL),
CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);