usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

13994

MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

1678

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

1755

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

1870

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

1900

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

2166

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/common/bnxe_clc.c

2669

REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_er.c

195

REG_WR(pdev, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);

usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/lm_hw_init_reset.c

2566

REG_WR(pdev,GRCBASE_MISC+MISC_REGISTERS_RESET_REG_2_SET,reset_reg_2_val);