MISC
{ "#define", ' ', MISC, NULL }, /* must be table entry 0 */
{ "#include", ' ', MISC, NULL }, /* must be table entry 1 */
{ "#define", ' ', MISC, NULL }, /* must be table entry 7 */
{ "\t", '\0', MISC, NULL }, /* must be table entry 9 */
{ "\n", '\0', MISC, NULL }, /* must be table entry 10 */
{ "sizeof", '\0', MISC, NULL },
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
ECORE_INIT_COMN(pdev, MISC);
#define init_misc_port( pdev) ECORE_INIT_PORT(pdev, MISC)
#define init_misc_func(pdev) ECORE_INIT_FUNC(pdev, MISC)
(void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, MISC), &misc);
(((msr) >= IA32_MSR_MC(0, CTL) && (msr) <= IA32_MSR_MC(10, MISC)) || \
mcrp->cmr_msrnum = IA32_MSR_MC(mib->mc_bank, MISC);