Symbol: MII_VENDOR
usr/src/uts/common/io/bge/bge_hw.h
1643
#define MII_EXT_CONTROL MII_VENDOR(0)
usr/src/uts/common/io/bge/bge_hw.h
1644
#define MII_EXT_STATUS MII_VENDOR(1)
usr/src/uts/common/io/bge/bge_hw.h
1645
#define MII_RCV_ERR_COUNT MII_VENDOR(2)
usr/src/uts/common/io/bge/bge_hw.h
1646
#define MII_FALSE_CARR_COUNT MII_VENDOR(3)
usr/src/uts/common/io/bge/bge_hw.h
1647
#define MII_RCV_NOT_OK_COUNT MII_VENDOR(4)
usr/src/uts/common/io/bge/bge_hw.h
1648
#define MII_AUX_CONTROL MII_VENDOR(8)
usr/src/uts/common/io/bge/bge_hw.h
1649
#define MII_AUX_STATUS MII_VENDOR(9)
usr/src/uts/common/io/bge/bge_hw.h
1650
#define MII_INTR_STATUS MII_VENDOR(10)
usr/src/uts/common/io/bge/bge_hw.h
1651
#define MII_INTR_MASK MII_VENDOR(11)
usr/src/uts/common/io/bge/bge_hw.h
1652
#define MII_HCD_STATUS MII_VENDOR(13)
usr/src/uts/common/io/bge/bge_hw.h
1654
#define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */
usr/src/uts/common/io/mii/mii_cicada.c
37
#define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2)
usr/src/uts/common/io/mii/mii_cicada.c
40
#define MII_CICADA_10BASET_CONTROL MII_VENDOR(6)
usr/src/uts/common/io/mii/mii_cicada.c
43
#define MII_CICADA_EXT_CONTROL MII_VENDOR(7)
usr/src/uts/common/io/mii/mii_cicada.c
50
#define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12)
usr/src/uts/common/io/mii/mii_intel.c
39
#define MII_82555_SPCL_CONTROL MII_VENDOR(1)
usr/src/uts/common/io/mii/mii_marvell.c
107
#define MVPHY_INTST MII_VENDOR(3) /* Interrupt status */
usr/src/uts/common/io/mii/mii_marvell.c
109
#define MVPHY_EPSC MII_VENDOR(4) /* Ext. phy specific control */
usr/src/uts/common/io/mii/mii_marvell.c
116
#define MVPHY_EADR MII_VENDOR(6) /* Extended address */
usr/src/uts/common/io/mii/mii_marvell.c
118
#define MVPHY_LED_PSEL MII_VENDOR(6) /* 88E3016 */
usr/src/uts/common/io/mii/mii_marvell.c
139
#define MVPHY_PAGE_ADDR MII_VENDOR(13)
usr/src/uts/common/io/mii/mii_marvell.c
140
#define MVPHY_PAGE_DATA MII_VENDOR(14)
usr/src/uts/common/io/mii/mii_marvell.c
143
#define MVPHY_EPSS MII_VENDOR(11) /* Ext. phy specific status */
usr/src/uts/common/io/mii/mii_marvell.c
163
PHY_SET(ph, MII_VENDOR(12), 0x0001);
usr/src/uts/common/io/mii/mii_marvell.c
37
#define MVPHY_PSC MII_VENDOR(0) /* PHY specific control */
usr/src/uts/common/io/mii/mii_marvell.c
88
#define MVPHY_INTEN MII_VENDOR(2) /* Interrupt enable */
usr/src/uts/common/io/mii/mii_natsemi.c
57
PHY_SET(ph, MII_VENDOR(7), (1<<10) | (1<<8) | (1<<5));
usr/src/uts/common/io/mii/mii_realtek.c
105
s = phy_read(ph, MII_VENDOR(9));
usr/src/uts/common/io/mii/mii_realtek.c
78
s = phy_read(ph, MII_VENDOR(0));
usr/src/uts/common/io/nge/nge_chip.h
1358
#define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2)
usr/src/uts/common/io/nge/nge_chip.h
1361
#define MII_CICADA_10BASET_CONTROL MII_VENDOR(6)
usr/src/uts/common/io/nge/nge_chip.h
1364
#define MII_CICADA_EXT_CONTROL MII_VENDOR(7)
usr/src/uts/common/io/nge/nge_chip.h
1371
#define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12)
usr/src/uts/common/io/rge/rge_hw.h
497
#define MII_EXT_CONTROL MII_VENDOR(0)
usr/src/uts/common/io/rge/rge_hw.h
498
#define MII_EXT_STATUS MII_VENDOR(1)
usr/src/uts/common/io/rge/rge_hw.h
499
#define MII_RCV_ERR_COUNT MII_VENDOR(2)
usr/src/uts/common/io/rge/rge_hw.h
500
#define MII_FALSE_CARR_COUNT MII_VENDOR(3)
usr/src/uts/common/io/rge/rge_hw.h
501
#define MII_RCV_NOT_OK_COUNT MII_VENDOR(4)
usr/src/uts/common/io/rge/rge_hw.h
502
#define MII_AUX_CONTROL MII_VENDOR(8)
usr/src/uts/common/io/rge/rge_hw.h
503
#define MII_AUX_STATUS MII_VENDOR(9)
usr/src/uts/common/io/rge/rge_hw.h
504
#define MII_INTR_STATUS MII_VENDOR(10)
usr/src/uts/common/io/rge/rge_hw.h
505
#define MII_INTR_MASK MII_VENDOR(11)
usr/src/uts/common/io/rge/rge_hw.h
506
#define MII_HCD_STATUS MII_VENDOR(13)
usr/src/uts/common/io/rge/rge_hw.h
508
#define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */
usr/src/uts/common/io/rtls/rtls.c
1928
case MII_VENDOR(0):
usr/src/uts/common/sys/nxge/nxge_mii.h
48
#define NXGE_MII_SHADOW MII_VENDOR(0xc)
usr/src/uts/common/sys/nxge/nxge_mii.h
50
#define NXGE_MII_MODE_CONTROL_REG MII_VENDOR(0xf)