MII_TG3_DSP_RW_PORT

2510

tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);

252

err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);

335

tg3_writephy(tp, MII_TG3_DSP_RW_PORT,

361

tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);

362

tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);

372

tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);

373

tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);

394

tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);

438

tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);

450

tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);