usr/src/uts/common/io/bfe/bfe.c

1438

v = (bfe->bfe_mii_bmsr & MII_STATUS_100_BASE_T4) != 0;

usr/src/uts/common/io/bfe/bfe.c

609

if (bmsr & MII_STATUS_100_BASE_T4) {

usr/src/uts/common/io/mii/mii.c

1701

ph->phy_cap_100_t4 = !!(bmsr & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/mii/mii.c

1729

if (bmsr & MII_STATUS_100_BASE_T4) {

usr/src/uts/common/io/mxfe/mxfe.c

1290

if (bmsr & MII_STATUS_100_BASE_T4) {

usr/src/uts/common/io/mxfe/mxfe.c

1344

if (!(bmsr & MII_STATUS_100_BASE_T4)) {

usr/src/uts/common/io/sfe/sfe_mii.h

77

(MII_STATUS_100_BASE_T4 | \

usr/src/uts/common/io/sfe/sfe_util.c

3452

val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/sfe/sfe_util.c

3672

if (val && (dp->mii_status & MII_STATUS_100_BASE_T4) == 0) {

usr/src/uts/common/io/sfe/sfe_util.c

3803

SETFUNC((dp->mii_status & MII_STATUS_100_BASE_T4) &&

usr/src/uts/common/io/sfe/sfe_util.c

4013

if (dp->mii_status & MII_STATUS_100_BASE_T4) {

usr/src/uts/common/io/sfe/sfe_util.c

4512

val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/sfe/sfe_util.c

4932

dp->anadv_100t4 &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/usbgem/usbgem.c

2505

BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/usbgem/usbgem.c

2988

if (dp->mii_status & MII_STATUS_100_BASE_T4) {

usr/src/uts/common/io/usbgem/usbgem.c

3480

val = BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/usbgem/usbgem.c

4532

dp->anadv_100t4 &= BOOLEAN(dp->mii_status & MII_STATUS_100_BASE_T4);

usr/src/uts/common/io/usbgem/usbgem_mii.h

108

(MII_STATUS_100_BASE_T4 | \

usr/src/uts/common/io/vr/vr.c

2349

v = (vrp->chip.mii.status & MII_STATUS_100_BASE_T4) != 0;

usr/src/uts/common/io/vr/vr.c

3334

MII_STATUS_100_BASE_T4) != 0;

usr/src/uts/common/io/vr/vr.c

755

if ((vrp->chip.mii.status & MII_STATUS_100_BASE_T4) == 0)

usr/src/uts/intel/io/dnet/dnet_mii.c

196

MII_STATUS_100_BASE_T4)) && phydata->fix_speed == 0) {