MII_REG
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl2),
MII_REG(serdes_reg_t, mii_aneg_nxt_pg_xmit1),
MII_REG(serdes_reg_t, mii_aneg_nxt_pg_xmit1),
MII_REG(serdes_reg_t, mii_aneg_advert),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_ctrl),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
MII_REG(serdes_reg_t, mii_ctrl),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_ctrl),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl3),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_stat1),
MII_REG(serdes_reg_t, mii_status),
MII_REG(serdes_reg_t, mii_aneg_nxt_pg_rcv2),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3),
0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3),
MII_REG(serdes_reg_t, mii_block_addr),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl3),
MII_REG(serdes_reg_t, mii_block_addr),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_ctrl),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl1),
0x10+MII_REG(serdes_tx_misc_reg_t, mii_txactl1),
MII_REG(serdes_reg_t, mii_phy_id_msb),
MII_REG(serdes_reg_t, mii_phy_id_lsb),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_digital3_reg_t, mii_digctl_3_0),
MII_REG(serdes_reg_t, mii_block_addr),
0x10+MII_REG(serdes_digital_reg_t, mii_1000x_ctl1),
MII_REG(serdes_reg_t, mii_aneg_nxt_pg_rcv1), &miireg);