MII_CONTROL
if(sis900_mdio_read(phy_addr, MII_CONTROL) & MII_CNTL_FDX)
case MII_CONTROL:
case MII_CONTROL:
atge_mii_write(atgep, phyaddr, MII_CONTROL, MII_CONTROL_RESET);
atge_mii_write(atgep, phyaddr, MII_CONTROL,
if (reg == MII_CONTROL) {
bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_RESET);
if (bfe_read_phy(bfe, MII_CONTROL) &
bfe_write_phy(bfe, MII_CONTROL, MII_CONTROL_PWRDN |
bfe_write_phy(bfe, MII_CONTROL, 0);
bfe_write_phy(bfe, MII_CONTROL, 0);
bfe_write_phy(bfe, MII_CONTROL, bmcr);
bmcr = bfe_read_phy(bfe, MII_CONTROL);
{ MII_CONTROL, "mii_control" },
bge_mii_put16(bgep, MII_CONTROL, control);
bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
control = bge_mii_get16(bgep, MII_CONTROL);
bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN);
PHY_CLR(ph, MII_CONTROL,
PHY_SET(ph, MII_CONTROL, MII_CONTROL_RESET);
if ((phy_read(ph, MII_CONTROL) & MII_CONTROL_RESET) == 0) {
phy_write(ph, MII_CONTROL, MII_CONTROL_ISOLATE);
phy_write(ph, MII_CONTROL, bmcr);
PHY_SET(ph, MII_CONTROL, MII_CONTROL_PWRDN);
phy_write(ph, MII_CONTROL, bmcr & ~(MII_CONTROL_RSAN));
phy_write(ph, MII_CONTROL, bmcr);
control = phy_read(ph, MII_CONTROL);
reg = phy_read(ph, MII_CONTROL);
phy_write(ph, MII_CONTROL, reg);
mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, MII_CONTROL_RESET);
if (mxfe_miiread(mxfep, phyaddr, MII_CONTROL) &
bmcr = mxfe_miiread(mxfep, phyaddr, MII_CONTROL);
mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, bmcr);
bmcr = mxfe_miiread(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL);
mxfe_miiwrite(mxfep, mxfep->mxfe_phyaddr, MII_CONTROL,
control = nge_mii_get16(ngep, MII_CONTROL);
nge_mii_put16(ngep, MII_CONTROL, control);
control = nge_mii_get16(ngep, MII_CONTROL);
control = nge_mii_get16(ngep, MII_CONTROL);
nge_mii_put16(ngep, MII_CONTROL, control);
control = nge_mii_get16(ngep, MII_CONTROL);
nge_mii_put16(ngep, MII_CONTROL, control);
control = nge_mii_get16(ngep, MII_CONTROL);
nge_mii_put16(ngep, MII_CONTROL, control);
case MII_CONTROL:
case MII_CONTROL:
control = rge_mii_get16(rgep, MII_CONTROL);
rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
control = rge_mii_get16(rgep, MII_CONTROL);
rge_mii_put16(rgep, MII_CONTROL, control);
case MII_CONTROL:
case MII_CONTROL:
val = gem_mii_read(dp, MII_CONTROL);
gem_mii_write(dp, MII_CONTROL, 0);
val = gem_mii_read(dp, MII_CONTROL);
val = gem_mii_read(dp, MII_CONTROL);
gem_mii_write(dp, MII_CONTROL, val);
gem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET);
val = gem_mii_read(dp, MII_CONTROL) &
gem_mii_write(dp, MII_CONTROL,
gem_mii_write(dp, MII_CONTROL, 0);
gem_mii_write(dp, MII_CONTROL, 0);
gem_mii_write(dp, MII_CONTROL, 0);
gem_mii_read(dp, MII_CONTROL), MII_CONTROL_BITS,
case MII_CONTROL:
case MII_CONTROL:
val = usbgem_mii_read(dp, MII_CONTROL, &err);
usbgem_mii_write(dp, MII_CONTROL, 0, &err);
val = usbgem_mii_read(dp, MII_CONTROL, &err);
val = usbgem_mii_read(dp, MII_CONTROL, &err);
val = usbgem_mii_read(dp, MII_CONTROL, &err);
usbgem_mii_write(dp, MII_CONTROL, val, &err);
usbgem_mii_write(dp, MII_CONTROL, MII_CONTROL_RESET, &err);
val = usbgem_mii_read(dp, MII_CONTROL, &err) &
usbgem_mii_write(dp, MII_CONTROL,
usbgem_mii_write(dp, MII_CONTROL, 0, &err);
usbgem_mii_write(dp, MII_CONTROL, 0, &err);
usbgem_mii_read(dp, MII_CONTROL, &err), MII_CONTROL_BITS,
vr_phy_write(vrp, MII_CONTROL, vrp->chip.mii.control);
vr_phy_read(vrp, MII_CONTROL, &vrp->chip.mii.control);
mac->mii_read(dip, phy, MII_CONTROL);
mac->mii_read(dip, phy, MII_CONTROL), status);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL,
control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
control = mac->mii_read(mac->mii_dip, phy, MII_CONTROL);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
mac->mii_write(mac->mii_dip, phy, MII_CONTROL, phyd->control);
mac->mii_write(dip, phy, MII_CONTROL, phyd->control|MII_CONTROL_RSAN);