Symbol: MII_ABILITY_100BASE_T4
usr/src/uts/common/io/bfe/bfe.c
1514
v = (bfe->bfe_mii_anlpar & MII_ABILITY_100BASE_T4) != 0;
usr/src/uts/common/io/bfe/bfe.c
567
anar &= ~(MII_ABILITY_100BASE_T4 |
usr/src/uts/common/io/bfe/bfe.c
612
anar |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/bfe/bfe.c
616
anar |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/bfe/bfe.c
787
} else if (anar & anlpar & MII_ABILITY_100BASE_T4) {
usr/src/uts/common/io/mii/mii.c
1338
anar |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/mii/mii.c
1541
ph->phy_lp_100_t4 = !!(lpar & MII_ABILITY_100BASE_T4);
usr/src/uts/common/io/mxfe/mxfe.c
1339
anar &= ~(MII_ABILITY_100BASE_T4 |
usr/src/uts/common/io/mxfe/mxfe.c
1371
anar |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/mxfe/mxfe.c
1537
} else if (anar & anlpar & MII_ABILITY_100BASE_T4) {
usr/src/uts/common/io/mxfe/mxfe.c
2792
*val = (mxfep->mxfe_anlpar & MII_ABILITY_100BASE_T4) ? 1 : 0;
usr/src/uts/common/io/sfe/sfe_mii.h
103
(MII_ABILITY_100BASE_T4 | \
usr/src/uts/common/io/sfe/sfe_util.c
2143
val |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/sfe/sfe_util.c
2514
} else if (val & MII_ABILITY_100BASE_T4) {
usr/src/uts/common/io/sfe/sfe_util.c
3532
val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4);
usr/src/uts/common/io/sfe/sfe_util.c
4520
val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4);
usr/src/uts/common/io/usbgem/usbgem.c
1100
val |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/usbgem/usbgem.c
1531
} else if ((val & MII_ABILITY_100BASE_T4)) {
usr/src/uts/common/io/usbgem/usbgem.c
3488
val = BOOLEAN(dp->mii_lpable & MII_ABILITY_100BASE_T4);
usr/src/uts/common/io/usbgem/usbgem_mii.h
153
(MII_ABILITY_100BASE_T4 | \
usr/src/uts/common/io/vr/vr.c
2309
v = (vrp->chip.mii.anadv & MII_ABILITY_100BASE_T4) != 0;
usr/src/uts/common/io/vr/vr.c
2443
v = (vrp->chip.mii.lpable & MII_ABILITY_100BASE_T4) != 0;
usr/src/uts/common/io/vr/vr.c
2745
} else if ((mask & MII_ABILITY_100BASE_T4) != 0) {
usr/src/uts/common/io/vr/vr.c
3205
MII_ABILITY_100BASE_T4) != 0;
usr/src/uts/common/io/vr/vr.c
3239
MII_ABILITY_100BASE_T4) != 0;
usr/src/uts/common/io/vr/vr.c
3474
~MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/vr/vr.c
3477
MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/vr/vr.c
723
vrp->param.anadv_en |= MII_ABILITY_100BASE_T4;
usr/src/uts/common/io/vr/vr.c
756
vrp->param.an_phymask &= ~MII_ABILITY_100BASE_T4;
usr/src/uts/intel/io/dnet/dnet_mii.c
830
} else if (mask & MII_ABILITY_100BASE_T4) {
usr/src/uts/intel/io/dnet/dnet_mii.c
956
} else if (mask & MII_ABILITY_100BASE_T4) {