Symbol: MCREG_FIELD_CMN
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
138
MCREG_FIELD_CMN(&scrubctl, DcacheScrub));
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
142
MCREG_FIELD_CMN(&scrubctl, L2Scrub));
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
146
MCREG_FIELD_CMN(&scrubctl, DcacheScrub) = ao_scrub_rate_dcache;
usr/src/uts/i86pc/cpu/amd_opteron/ao_cpu.c
147
MCREG_FIELD_CMN(&scrubctl, L2Scrub) = ao_scrub_rate_l2cache;
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1081
if (MCREG_FIELD_CMN(&scrubctl, DramScrub) == 0)
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1421
return (MCREG_FIELD_CMN(&scrubctl, DramScrub) !=
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1428
MCREG_FIELD_CMN(&scrubctl, DramScrub) = AMD_NB_SCRUBCTL_RATE_NONE;
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1436
MCREG_FIELD_CMN(&dalo, ScrubReDirEn) = 1;
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1437
MCREG_FIELD_CMN(&dalo, ScrubAddrLo) =
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1440
MCREG_FIELD_CMN(&dahi, ScrubAddrHi) =
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
1507
MCREG_FIELD_CMN(&scrubctl, DramScrub) = mc_scrub_rate_dram;
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
354
(void) nvlist_add_uint32(nvl, "NodeId", MCREG_FIELD_CMN(nip, NodeId));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
356
(void) nvlist_add_uint32(nvl, "SbNode", MCREG_FIELD_CMN(nip, SbNode));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
357
(void) nvlist_add_uint32(nvl, "LkNode", MCREG_FIELD_CMN(nip, LkNode));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
361
(void) nvlist_add_uint32(nvl, "C0Unit", MCREG_FIELD_CMN(uip, C0Unit));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
362
(void) nvlist_add_uint32(nvl, "C1Unit", MCREG_FIELD_CMN(uip, C1Unit));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
363
(void) nvlist_add_uint32(nvl, "McUnit", MCREG_FIELD_CMN(uip, McUnit));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
364
(void) nvlist_add_uint32(nvl, "HbUnit", MCREG_FIELD_CMN(uip, HbUnit));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
365
(void) nvlist_add_uint32(nvl, "SbLink", MCREG_FIELD_CMN(uip, SbLink));
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
369
BCRte[i] = MCREG_FIELD_CMN(htrp, BCRte);
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
370
RPRte[i] = MCREG_FIELD_CMN(htrp, RPRte);
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
371
RQRte[i] = MCREG_FIELD_CMN(htrp, RQRte);
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
699
if (MCREG_FIELD_CMN(&limreg, DRAMLimiti) != 0 &&
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
700
MCREG_FIELD_CMN(&limreg, DstNode) == nodeid &&
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
701
(MCREG_FIELD_CMN(&basereg, WE) || MCREG_FIELD_CMN(&basereg, RE))) {
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
704
mcp->mcp_ilen = MCREG_FIELD_CMN(&basereg, IntlvEn);
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
705
mcp->mcp_ilsel = MCREG_FIELD_CMN(&limreg, IntlvSel);
usr/src/uts/intel/io/mc-amd/mcamd_drv.c
718
if (MCREG_FIELD_CMN(&hole, DramHoleValid))
usr/src/uts/intel/sys/mc_amd.h
342
#define HT_COHERENTNODES(up) (MCREG_FIELD_CMN(up, NodeCnt) + 1)
usr/src/uts/intel/sys/mc_amd.h
343
#define HT_SYSTEMCORECOUNT(up) (MCREG_FIELD_CMN(up, CpuCnt) + 1)
usr/src/uts/intel/sys/mc_amd.h
377
#define MC_DRAMBASE(up) ((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24)
usr/src/uts/intel/sys/mc_amd.h
396
((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 | \
usr/src/uts/intel/sys/mc_amd.h
397
(MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0))
usr/src/uts/intel/sys/mc_amd.h
414
#define MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24)