usr/src/uts/common/io/chxge/com/mc5.c

325

t1_write_reg_4(adap, A_MC5_POPEN_DATA_WR_CMD, MC5_IDT_CMD_WRITE);

usr/src/uts/common/io/chxge/com/mc5.c

326

t1_write_reg_4(adap, A_MC5_POPEN_MASK_WR_CMD, MC5_IDT_CMD_WRITE);

usr/src/uts/common/io/chxge/com/mc5.c

335

t1_write_reg_4(adap, A_MC5_DATA_WRITE_CMD, MC5_IDT_CMD_WRITE);

usr/src/uts/common/io/chxge/com/mc5.c

343

if (mc5_write(adap, MC5_IDT_LAR_ADR0, MC5_IDT_CMD_WRITE))

usr/src/uts/common/io/chxge/com/mc5.c

348

if (mc5_write(adap, MC5_IDT_SSR0_ADR0, MC5_IDT_CMD_WRITE) ||

usr/src/uts/common/io/chxge/com/mc5.c

349

mc5_write(adap, MC5_IDT_SSR1_ADR0, MC5_IDT_CMD_WRITE))

usr/src/uts/common/io/chxge/com/mc5.c

362

MC5_IDT_CMD_WRITE))

usr/src/uts/common/io/chxge/com/mc5.c

368

if (mc5_write(adap, MC5_IDT_SCR_ADR0, MC5_IDT_CMD_WRITE))

usr/src/uts/common/io/chxge/com/mc5.c

373

MC5_IDT_CMD_WRITE);