usr/src/uts/common/io/chxge/com/fpga_defs.h

239

#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)

usr/src/uts/common/io/chxge/com/fpga_defs.h

240

#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)

usr/src/uts/common/io/chxge/com/fpga_defs.h

241

#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)

usr/src/uts/common/io/chxge/com/fpga_defs.h

242

#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)

usr/src/uts/common/io/chxge/com/fpga_defs.h

243

#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)

usr/src/uts/common/io/chxge/com/fpga_defs.h

244

#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)

usr/src/uts/common/io/chxge/com/fpga_defs.h

245

#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)

usr/src/uts/common/io/chxge/com/fpga_defs.h

246

#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)

usr/src/uts/common/io/chxge/com/fpga_defs.h

247

#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)

usr/src/uts/common/io/chxge/com/fpga_defs.h

248

#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)

usr/src/uts/common/io/chxge/com/fpga_defs.h

249

#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)

usr/src/uts/common/io/chxge/com/fpga_defs.h

250

#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)

usr/src/uts/common/io/chxge/com/fpga_defs.h

251

#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)

usr/src/uts/common/io/chxge/com/fpga_defs.h

252

#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)

usr/src/uts/common/io/chxge/com/fpga_defs.h

253

#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)