usr/src/uts/common/disp/disp_lock.c

141

while (lp == *tlpp && LOCK_HELD(lp)) {

usr/src/uts/common/disp/disp_lock.c

176

while (lp == *tlpp && LOCK_HELD(lp)) {

usr/src/uts/common/dtrace/dtrace.c

4108

regs[rd] = LOCK_HELD(&m.mi.m_spin.m_spinlock);

usr/src/uts/common/os/dumpsubr.c

1649

while (LOCK_HELD(lp) || !lock_spin_try(lp)) {

usr/src/uts/common/os/mutex.c

541

return (LOCK_HELD(&lp->m_spin.m_spinlock));

usr/src/uts/common/os/mutex.c

662

while (LOCK_HELD(lp) || !lock_spin_try(lp)) {

usr/src/uts/common/os/mutex.c

701

while (LOCK_HELD(lp)) {

usr/src/uts/common/os/turnstile.c

333

ASSERT(LOCK_HELD(wlp));

usr/src/uts/common/os/turnstile.c

372

while (olp == *olpp && LOCK_HELD(olp)) {

usr/src/uts/common/sys/t_lock.h

79

#define DISP_LOCK_HELD(lp) LOCK_HELD((lock_t *)(lp))

usr/src/uts/common/sys/thread.h

500

#define SWAP_OK(t) (!LOCK_HELD(&(t)->t_lock))

usr/src/uts/i86pc/io/apix/apix.c

1577

ASSERT(LOCK_HELD(&apix_lock));

usr/src/uts/i86pc/io/apix/apix.c

1642

ASSERT(LOCK_HELD(&apix_lock));

usr/src/uts/i86pc/io/apix/apix.c

1766

ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));

usr/src/uts/i86pc/io/apix/apix.c

1804

ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));

usr/src/uts/i86pc/io/apix/apix.c

766

ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));

usr/src/uts/i86pc/io/apix/apix.c

799

ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));

usr/src/uts/i86pc/io/apix/apix_utils.c

1471

ASSERT(LOCK_HELD(&apix_lock) && count > 0);

usr/src/uts/i86pc/io/apix/apix_utils.c

1805

ASSERT(LOCK_HELD(&apix_lock));

usr/src/uts/i86pc/io/mp_platform_misc.c

1667

ASSERT(LOCK_HELD(&apic_ioapic_lock));

usr/src/uts/i86pc/sys/apix.h

197

#define APIX_CPU_LOCK_HELD(cpuid) LOCK_HELD(&apixs[(cpuid)]->x_lock)

usr/src/uts/i86xpv/io/psm/mp_platform_xpv.c

1589

ASSERT(LOCK_HELD(&apic_ioapic_lock));

usr/src/uts/intel/os/smt.c

348

ASSERT(LOCK_HELD(&smt->cs_lock));