Symbol: DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
37733
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
34431
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 Indicates whether Ethernet over GRE header is expected in packet payload. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
37720
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
37720
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
37720
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.