DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0xd24cUL //ACCESS:RW DataWidth:0xa Multi Field Register
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL //Access:RW DataWidth:0xa // Multi Field Register.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL //Access:RW DataWidth:0xa Multi Field Register. Chips: BB_A0 BB_B0 K2
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL //Access:RW DataWidth:0xa // Multi Field Register.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL //Access:RW DataWidth:0xa // Multi Field Register.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL //Access:RW DataWidth:0xa // Multi Field Register.