DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0xd2acUL //ACCESS:RW DataWidth:0x8 Description: The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 2 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL //Access:RW DataWidth:0xb // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL //Access:RW DataWidth:0xa The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message. Chips: BB_A0 BB_B0 K2
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL //Access:RW DataWidth:0xa // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL //Access:RW DataWidth:0xb // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_set_cnstr_offseti[2:0]] and frame[32*trigger_state_set_cnstr_offseti[2:0]].
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL //Access:RW DataWidth:0xa // The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.