DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0xd18cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>. Chips: BB_A0 BB_B0 K2
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
#define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.