Symbol: DBG_REG_TRIGGER_STATE_MSG_LENGTH_0
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
4030
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0xd438UL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34802
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31298
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL //Access:RW DataWidth:0x8 Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34770
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34770
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34770
#define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when trigger_state_msg_length_eni = 1.