Symbol: DBG_REG_TRIGGER_STATE_ID_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34445
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL //Access:RW DataWidth:0x4 // Number of ID that should be triggered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30941
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL //Access:RW DataWidth:0x3 Number of ID that should be triggerd. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34413
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL //Access:RW DataWidth:0x3 // Number of ID that should be triggerd.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34413
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL //Access:RW DataWidth:0x4 // Number of ID that should be triggered. For HW block only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggered (0 - STORM A; 1 - STORM B). Bits[2:0] designate STORM ID.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34413
#define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL //Access:RW DataWidth:0x3 // Number of ID that should be triggerd.