DBG_REG_TRIGGER_ENABLE
#define DBG_REG_TRIGGER_ENABLE 0xd010UL //ACCESS:RW DataWidth:0x1 Description: (a) 0 - trigger machine is off (all data will bypass the triggering machine) in this mode trigger_event is never asserted. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode.
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode. Chips: BB_A0 BB_B0 K2
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode.
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode.
#define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode.