Symbol: DBG_REG_TIMESTAMP_VALID_EN
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34932
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL //Access:RW DataWidth:0x7 // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when bit[0] is set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[3] is set or bit[3] is set and valid[4] is set or bit[4] is set and valid[5] is set or bit[5] is set and valid[6] is set or bit[6] is set and valid[7] is set.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31428
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL //Access:RW DataWidth:0x3 Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when B0 is set and valid[1] is set or B1 is set and valid[2] is set or B2 is set and valid[3] is set. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34900
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL //Access:RW DataWidth:0x3 // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when B0 is set and valid[1] is set or B1 is set and valid[2] is set or B2 is set and valid[3] is set.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34900
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL //Access:RW DataWidth:0x7 // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when bit[0] is set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[3] is set or bit[3] is set and valid[4] is set or bit[4] is set and valid[5] is set or bit[5] is set and valid[6] is set or bit[6] is set and valid[7] is set.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34900
#define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL //Access:RW DataWidth:0x3 // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when B0 is set and valid[1] is set or B1 is set and valid[2] is set or B2 is set and valid[3] is set.