Symbol: DBG_REG_TIMESTAMP
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34929
#define DBG_REG_TIMESTAMP 0x010b4cUL //Access:RW DataWidth:0x20 // Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31425
#define DBG_REG_TIMESTAMP 0x010b4cUL //Access:RW DataWidth:0x20 Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34897
#define DBG_REG_TIMESTAMP 0x010b4cUL //Access:RW DataWidth:0x20 // Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34897
#define DBG_REG_TIMESTAMP 0x010b4cUL //Access:RW DataWidth:0x20 // Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34897
#define DBG_REG_TIMESTAMP 0x010b4cUL //Access:RW DataWidth:0x20 // Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.