Symbol: DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
4117
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0xd554UL //ACCESS:RW DataWidth:0x20 Description: Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34893
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL //Access:RW DataWidth:0x20 // Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31389
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL //Access:RW DataWidth:0x20 Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles). Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34861
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL //Access:RW DataWidth:0x20 // Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34861
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL //Access:RW DataWidth:0x20 // Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34861
#define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL //Access:RW DataWidth:0x20 // Number of valid cycles that should be recorded upon triggering event. NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).