Symbol: DBG_REG_FILTER_MSG_LENGTH
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
4113
#define DBG_REG_FILTER_MSG_LENGTH 0xd544UL //ACCESS:RW DataWidth:0x7 Description: Message length-1 in terms of numbers of cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc. (c) Applicable only when filter_msg_length_en = 1
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34887
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31383
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL //Access:RW DataWidth:0x8 Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34855
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34855
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34855
#define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycles. NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.