Symbol: DBG_REG_FILTER_CNSTR_OFFSET_0
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
4072
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0xd4e0UL //ACCESS:RW DataWidth:0x3 Description: The above value vector (data & frame) should be compared filter_cnstr_offseti / 2 cycles after start of message (0..3 cycles --> valid values: 0..7; The filtering is implemented according to the data on the first 4 cycles only) NOTE: (a) even though the comparison is for the first 4 cycles only; the messages length is up to 128 cycles.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34846
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31342
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL //Access:RW DataWidth:0x4 The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34814
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL //Access:RW DataWidth:0x4 // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34814
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start of message; filter_cnstr_offseti[2:0] represent the dword offset within a cycle.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34814
#define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL //Access:RW DataWidth:0x4 // The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.