Symbol: DBG_REG_ETHERNET_HDR_WIDTH
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34924
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL //Access:RW DataWidth:0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
31420
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL //Access:RW DataWidth:0x4 Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34892
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL //Access:RW DataWidth:0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34892
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL //Access:RW DataWidth:0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34892
#define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL //Access:RW DataWidth:0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.