DBG_REG_DEBUG_TARGET
#define DBG_REG_DEBUG_TARGET 0xc030UL //ACCESS:RW DataWidth:0x2 Description: debug only: These bits indicates the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI;
#define DBG_REG_DEBUG_TARGET 0x01005cUL //Access:RW DataWidth:0x2 // Debug only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
#define DBG_REG_DEBUG_TARGET 0x01005cUL //Access:RW DataWidth:0x2 Debug only: These bits indicates the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI;. Chips: BB_A0 BB_B0 K2
#define DBG_REG_DEBUG_TARGET 0x01005cUL //Access:RW DataWidth:0x2 // Debug only: These bits indicates the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI;.
#define DBG_REG_DEBUG_TARGET 0x01005cUL //Access:RW DataWidth:0x2 // Debug only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
#define DBG_REG_DEBUG_TARGET 0x01005cUL //Access:RW DataWidth:0x2 // Debug only: These bits indicates the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI;.