Symbol: DBG_REG_DBG_BLOCK_ON
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
3626
#define DBG_REG_DBG_BLOCK_ON 0xc064UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34429
#define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30925
#define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34397
#define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34397
#define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34397
#define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.