DBG_REG_CPU_TIMEOUT
#define DBG_REG_CPU_TIMEOUT 0xc060UL //ACCESS:RW DataWidth:0x1 Description: debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty
#define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.
#define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty. Chips: BB_A0 BB_B0 K2
#define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.
#define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.
#define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.