DBG_REG_CALENDAR_SLOT0
#define DBG_REG_CALENDAR_SLOT0 0xc008UL //ACCESS:RW DataWidth:0x4 Description: debug only: These bits are a client index for slot 0 in calendar as follows: 0b0000 - rx; 0b0001 - nm; 0b0010 - ulp; 0b0011 - tx; 0b0100 - cpt; 0b0101 - usem; 0b0110 - xsem; 0b0111 - tsem; 0b1000 - csem; 0b1001 - cpu; 0b1010 - joint HW; 0b1111 - None;
#define DBG_REG_CALENDAR_SLOT0 0x010014UL //Access:RW DataWidth:0x3 // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
#define DBG_REG_CALENDAR_SLOT0 0x010014UL //Access:RW DataWidth:0x3 Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none. Chips: BB_A0 BB_B0 K2
#define DBG_REG_CALENDAR_SLOT0 0x010014UL //Access:RW DataWidth:0x3 // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
#define DBG_REG_CALENDAR_SLOT0 0x010014UL //Access:RW DataWidth:0x3 // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.
#define DBG_REG_CALENDAR_SLOT0 0x010014UL //Access:RW DataWidth:0x3 // Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.