YSEM_REG_SYNC_DBG_EMPTY
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x2 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR debug FIFO of Core B
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x1 DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Chips: BB_A0 BB_B0 K2
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
#define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.