Symbol: XSDM_REG_OPERATION_GEN
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
23678
#define XSDM_REG_OPERATION_GEN 0x1664c4UL //ACCESS:W DataWidth:0x11 Description: Generate an operation after completion; bit-16 is AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and bits 4:0 are the T124Param[4:0]
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
66319
#define XSDM_REG_OPERATION_GEN 0xf80408UL //Access:W DataWidth:0x14 // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
60720
#define XSDM_REG_OPERATION_GEN 0xf80408UL //Access:W DataWidth:0x14 This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
64101
#define XSDM_REG_OPERATION_GEN 0xf80408UL //Access:W DataWidth:0x14 // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
64101
#define XSDM_REG_OPERATION_GEN 0xf80408UL //Access:W DataWidth:0x14 // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
64101
#define XSDM_REG_OPERATION_GEN 0xf80408UL //Access:W DataWidth:0x14 // This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.