XMAC_REG_CTRL_SA_HI
#define XMAC_REG_CTRL_SA_HI 0x2cUL //ACCESS:RW DataWidth:0x10 Description: Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC
#define XMAC_REG_CTRL_SA_HI 0x21002cUL //Access:RW DataWidth:0x10 Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC. Chips: BB_A0 BB_B0 K2