TSEM_REG_INT_TABLE
#define TSEM_REG_INT_TABLE 0x180400UL //ACCESS:RW DataWidth:0xf Description: Interrupt table Read and write access to it is not possible in the middle of the work
#define TSEM_REG_INT_TABLE 0x1710000UL //Access:RW DataWidth:0x1e // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[29] = Allocated per child; int_table[28] = Increment type; int_table[27:23] = Counter select; int_table[22] = Counter insert; int_table[21:17] = GapSel; int_table[16] = Monitor enable; int_table[15:0] = PRAM Address;
#define TSEM_REG_INT_TABLE 0x1710000UL //Access:RW DataWidth:0x15 Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address Chips: BB_A0 BB_B0 K2
#define TSEM_REG_INT_TABLE 0x1710000UL //Access:RW DataWidth:0x15 // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address
#define TSEM_REG_INT_TABLE 0x1710000UL //Access:RW DataWidth:0x15 // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address
#define TSEM_REG_INT_TABLE 0x1710000UL //Access:RW DataWidth:0x15 // Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address