Symbol: TM_REG_DBG_FORCE_VALID
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
45645
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
41532
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL //Access:RW DataWidth:0x4 DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift). Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
44640
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
44640
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
44640
#define TM_REG_DBG_FORCE_VALID 0x2c07b4UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift).